Power semiconductor devices are currently being used in many applications. Such power devices include high-voltage integrated circuits which typically include one or more high-voltage transistors, often on the same chip as low-voltage circuitry. A commonly used high-voltage component for these circuits is the lateral double diffused MOS transistor (LDMOS). LDMOS structures used in the high-voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. In general, these existing LDMOS structures are fabricated in a thick epitaxial layer of opposite conductivity type to the substrate or they use a thin epitaxial layer and apply the RESURF principle to equally distribute the applied drain voltage laterally across the silicon surface in the drift region of the device.
High-power applications have called for the use of such lateral double diffused MOS transistors primarily because they possess lower "on" resistance, R.sub.DS (on), faster switching speed, and lower gate drive power dissipation than their bi-polar counterparts. These devices have heretofore also been strongly associated with bi-polar based process flows when integrated into a Bi-CMOS environment.
However, the presence of circuitry for digital and power switching functions on a chip with analog circuitry poses significant problems for precision analog circuitry because of the resulting mixed signal environment. For instance, switching noise in the digital and power areas can often be coupled into the analog sections via the substrate. That is, power switching injects current into the substrate that "bounces" all the other circuitry on the chip; however, reducing the resistance of the power transistor minimizes this effect. Secondly, a more frequent problem is that the analog sections-operate with the dual supply bias-system while the digital portion utilizes a single supply bias scheme; this results in the need to do level shifting which complicates the design. One prior art technique uses a Bi-CMOS process with a unique isolation scheme such that the bi-polar layers can be used to construct a junction-isolated region to house any sensitive components.
The size and performance of the power IC devices (LDMOS devices) depends critically on a specific R.sub.DS (on) at a particular break-down voltage, BY, of the output devices. Since the field oxide thickness is usually limited by technological constraints, higher break-down voltages typically require more lightly doped layers. However, since the device on resistance, R.sub.DS (on), is proportional to the epitaxial layer resistivity, higher break-down voltages must generally be traded off for limited drive current capability. That is, the break-down voltage of the LDMOS transistor is optimized by adjusting the drift region epitaxial thickness but with increased resistivity due to more lightly doped layers; this optimization can also result from reduced surface fields (RESURF) techniques. However, the small drift region thickness required to obtain the optimum break-down voltage often results in an objectionable increase in the minimum on resistance, R.sub.DS (on), of RESURF devices.
The main objective of the design of the LDMOS device is to minimize "on" resistance, R.sub.DS (on), while still maintaining high break-down voltages. However, as noted earlier, these two electrical parameters tend to have conflicting requirements as far as processing variables such as epitaxial doping and thicknesses are concerned. Hence, the optimization of the LDMOS device is often a crucial step in the process design cycle.
Purely self-aligned LDMOS transistors, such as stand-alone devices fabricated by standard DMOS techniques, cannot be easily integrated into processes that include other low power devices because a layer of polysilicon (for the DMOS gate) is normally required early in the fabrication process to permit self-alignment of the source and backgate diffusions to the gate. The subsequent DMOS long source diffusion degrades a normal low power CMOS logic transistor fabricated during the same process. In addition, a purely photo-aligned device is difficult to control because the back gate leaves no marks for alignment and the channel length is dependent upon the alignment.
Heretofore most LDMOS structures built on a substrate along with one or more other device structures have been formed by first forming a high-voltage tank in the substrate. After the formation of the high-voltage tank a second low-voltage tank (typically used as the back gate) of opposite conductivity type to that of the first tank, was formed within the first high-voltage tank, and the active regions and gates were then aligned to these tanks. However, the alignment of these active regions and gates to the other existing structures, specifically, the high-voltage tank and the low-voltage tank is difficult. Current techniques use a hybrid of photo-alignment and self-alignment to fabricate these devices, such as taught in U.S. Pat. No. 5,242,841.
Most recently, LDMOS devices have been utilized in a single chip on a single substrate with a variety of logic devices, memory devices and other power devices capable of withstanding large transients. However, they also find use as a separate device for certain applications.
It is, therefore, desirable to be able to fabricate LDMOS devices that have an improved R.sub.DS (on) while maintaining a high break-down voltage. It is also desirable to be able to fabricate such an improved LDMOS device using steps in a process flow that are consistent with the fabrication of other high-power and low-power devices on a single chip.